The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a buried gate.
In a 60 nm DRAM process, a buried gate is formed in order to increase the integration of transistors in a cell, simplify the process and enhance device characteristics such as a leakage current.
A method for fabricating a buried gate is performed by forming a trench and burying a gate in the trench. Accordingly, the method can minimize interference between a bit line and gates, decrease the number of film stacks, and decrease a total capacitance of the entire cells, thereby improving refresh characteristics.
FIGS. 1A to 1E are cross-sectional views illustrating a method for fabricating a semiconductor device having a buried gate, in accordance with prior art.
Referring to FIG. 1A, a device isolation layer 12 is formed on a substrate 11, in which a cell region and a peripheral region are defined.
Thereafter, the substrate 11 corresponding to the cell region is etched using a hard mask layer 13 to form a trench 14 and then to form a first gate insulation layer 15 in the trench 14. Thereafter, a buried gate 16 partially filling the trench 14 is formed on the first gate insulation layer 15.
Referring to FIG. 1B, the hard mask layer 13 is removed, and then a sealing layer 17 sealing a top surface of the buried gate 16 is formed.
Thereafter, a peri (that is, peripheral) open process is performed to open a peripheral region such that the seal layer 17 is left only on the cell region.
Thereafter, a gate oxidation process is performed with respect to the peripheral region to form a second gate insulation layer 18.
Referring to FIG. 1C, a gate conductive layer 19 is formed on the second gate insulation layer 18, and then a process of forming a bit line contact hole 20 is performed for bit line contact at the cell region. As a result, the sealing layer 17 (see FIG. 1B) becomes a sealing pattern 17A partially exposing the substrate 11.
Referring to FIG. 1D, a metal layer is deposited such that the bit line contact hole 20 is filled, and then a hard mask layer is formed on the deposited metal layer.
Thereafter, a gate etch is performed which etches the hard mask layer, the metal layer, the gate conductive layer and the first gate insulation layer. As a result, a gate (hereinafter referred to as a ‘peri gate (PG)’) for a transistor of the peripheral region, including a second gate insulation layer pattern 18A, a gate conductive pattern 19A, a gate metal pattern 21B and a gate hard mask pattern 22B, stacked in the order named, is formed in the peripheral region. While the peri gate (PG) is formed, a bit line (BL), which also functions as a bit line contact and includes a bit line interconnection pattern 21A and a bit line hard mask pattern 22A stacked in the order named, is formed in the cell region.
Referring to FIG. 1E, an interlayer dielectric is formed on an entire surface of the substrate 11. Thereafter, a contact forming process for forming a storage node contact 24 in the cell region is performed by etching the interlayer dielectric. This contact forming process is performed even with respect to a surface of the substrate, so that the sealing pattern 17A (see FIG. 1D) and the interlayer dielectric are partially etched and become a final sealing pattern 17B and an interlayer dielectric 23.
In the foregoing prior art, after the buried gate 16 is formed in the cell region, the sealing process for preventing an oxidation of the buried gate 16 is performed by using the sealing layer 17. Thereafter, the gate oxidation and the gate conductive layer depositing process for forming the transistor of the peripheral region are performed by opening only the peripheral region. Thereafter, the cell region is again opened, and the contact etching process for forming the bit line contact hole is performed.
However, although the prior art seals the cell region by using the sealing layer 17, while the gate oxidation process is performed in the peripheral region, the prior art may prevent the buried gate 16 from being oxidized due to an oxygen source (See the reference symbol ‘A’ of FIG. 1B).
Also, since after the bit line (BL) is formed in the cell region, the storage node contact 24 is formed, thus it may be difficult to secure a contact open area for forming the storage node contact 24. In addition, since the contact open area is small, an interfacial resistance between the storage node contact and the substrate is increased.
Furthermore, in the prior art, since while the storage node contact process or the bit line contact process is performed, the substrate may be lost due to an over etch (see the reference symbol ‘B’ of FIG. 1C), GIDL (Gate Induced Drain Leakage) between the storage node contact and the buried gate is increased, and the possibility causing a self aligned contact fail may be increased.
To overcome the above problem, a method has been proposed that elevates a portion where a landing plug is formed by employing a hard mask layer, removing the hard mask layer, and forming a landing plug. However, this method has a difficulty in controlling a height of a contact above a predetermined height, since while the hard mask layer is removed, a contact widening occurs that increases the possibility of a bridge between contacts and an etch process; a CMP (Chemical Mechanical Polishing) process may also be performed in a mid-process.